1. Field of the Invention
The present invention relates to the fabrication of electrically-programmable read-only-memories (EPROMs) and "flash" memories and, in particular, to a method of controlling oxide thinning in the fabrication of an EPROM or flash array to prevent electrical shorts in the array and trenching of the bit line.
2. Description of the Related Art
An electrically-programmable read-only-memory (EPROM) and a "flash" memory are non-volatile memories which maintain data stored in the memory when power is removed. EPROM devices are erased by exposure to ultraviolet light. Flash memories add electrical erasure and reprogramming functionality to the non-volatility of the EPROM.
A virtual-ground, buried-bit line, EPROM or flash array are increased-density memories that realize the increased density by reducing the number of electrical contacts which are required by the array. In contrast with a conventional array, which forms a bit line contact for every two cells, the virtual-ground array forms a bit line contact for a larger number of cells, typically ranging from 16 to 64 cells.
FIG. 1 shows a plan diagram that illustrates a representation of a virtual-ground EPROM or flash array 10. As shown in FIG. 1, array 10 includes a number of columns of buried bit lines BL1-BLn which alternately represent the drain and the source of the memory cells 14 of array 10. Array 10 also includes a number of word lines WL1-WLn which orthogonally intersect each of the buried bit lines BL1-BLn. Finally, electrical contacts 18 are formed on each end of the buried bit lines BL1-BLn. Thus, the electrical contacts form a bit line contact for every n cells.
FIGS. 2A-2H show a cross-sectional diagram taken along lines 2A--2A of FIG. 1 that illustrates a process flow for the fabrication of the virtual ground, buried bit line array 10. As shown in FIG. 2A, the array is conventionally fabricated by first forming a layer of gate oxide 22 on a P-type silicon substrate 20. This is followed by the deposition of a layer of polysilicon (polyl) 24 and the formation of an overlying layer of oxide-nitride-oxide (ONO) 26. Next, an ONO/polyl mask is formed over the layer of ONO 26 and patterned to define rows of ONO/polyl strips 28. The unmasked layer of ONO 26 and the corresponding underlying layer of polyl 24 are then etched until the underlying layer of gate oxide 22 is exposed.
Referring to FIG. 2B, after the rows of ONO/polyl strips 28 have been formed, arsenic is implanted to define the N+ buried bit lines 30 of the virtual-ground array. Following this, the ONO/polyl mask is stripped, and a thin layer of edge oxide 32 is grown on each ONO/polyl strip 28 and the exposed layer of gate oxide 22 between the rows of ONO/polyl strips 28. As shown in FIG. 2B and as well known in the art, substantially no edge oxide 32 is grown on the layer of ONO 26 due to the lack of an oxidizing material.
Referring to FIG. 2C, once the thin layer of edge oxide 32 has been formed, a layer of differential oxide 34 is grown over the layer of edge oxide 32. As with the layer of edge oxide 32, substantially no differential oxide 34 is grown over the layer of ONO 26.
As shown in FIG. 2C, two problems arise from the formation of the layer of differential oxide 34. First, the structural stress which is present at the corners of semiconductor devices causes oxide thinning to occur which results in the formation of recesses 36. Second, oxide wedges 38 are formed as a result of the oxidation of a portion of the layer of polyl 24 at the outer boundary between the layers of polyl 24 and ONO 26.
As described in greater detail below, the recesses 36 and the oxide wedges 38 in turn cause the formation of poly2 remnants and polyl stringers, respectively. The poly2 remnants may cause word line to word line shorts while the polyl stringers may cause polyl floating gate to polyl floating gate shorts. Further, the recesses 36 define the minimum thickness of the layer of differential oxide 34 that is formed over the N+ buried bit lines 30. Thus, as also described in greater detail below, the recesses 36 can cause portions of the N+ buried bit lines 30 to be trenched in subsequent etching steps.
Referring to FIG. 2D, after the layer of differential oxide 34 has been formed, a second layer of polysilicon (poly2) 40 is deposited on the layer of differential oxide 34. Once the layer of poly2 40 has been deposited, the word lines WL1-WLn of FIG. 1 are formed.
FIG. 3 shows a perspective view taken between lines 3A--3A and lines 3AA--3AA of FIG. 1 that illustrates the ideal formation of word lines WL1 and WL2. As shown in FIGS. 1, 2, and 3, the word lines WL1 and WL2 are ideally formed by removing the layers of poly2 40, ONO 26, and polyl 24 that have been formed in the regions 42 between the word lines WL1 and WL2.
Referring again to FIG. 2D, after the layer of poly2 40 has been deposited, a poly2 mask (not shown) is formed on the array to define the word lines. Once the poly2 mask has been formed, the unmasked areas of the layer of poly2 40 are anisotropically etched until the layers of differential oxide 34 and ONO 26 are exposed. The etching chemistries which are typically utilized to etch poly2 have a high-selectivity with respect to differential oxide and ONO. Thus, when the layer of poly2 40 is etched, the layers of differential oxide 34 and ONO 26 remain substantially intact.
Referring to FIG. 2E, since the anisotropic etch is essentially a vertical etch, poly2 remnants 44 are formed in the recesses 36 because a portion 46 of the layer of differential oxide 34 effectively functions as a mask. As stated above and as shown in FIG. 4, the poly2 remnants 44 can cause shorts between adjacent poly2 word lines such as word lines WL1 and WL2.
After the layer of poly2 40 has been removed, the layer of ONO 26 and the minimal layers of differential oxide 34 and edge oxide 32 are etched with an etching chemistry which typically has a relatively high-selectivity between the remaining layer of poly and the layers of differential oxide 34, edge oxide 32, and ONO 26.
As shown in FIG. 2F, to prevent this etching step from exposing a portion of the N+ buried bit lines 30 and subsequently removing a portion of the N+ buried bit lines 30 during the following polyl etch step, the minimum thickness R of the combined layers of differential oxide 34 and edge oxide 32, as shown in FIG. 2E, must be greater than the combined thickness T of the layer of ONO 26 and an oxide wedge 38.
As shown in FIGS. 2G and 5, the principal disadvantage of failing to remove the oxide wedges 38 is the formation of polyl stringers 48 which, as stated above, also can result in shorts between the polyl floating gates of adjacent memory cells 14. After the layers of differential oxide 34, edge oxide 32, and ONO 26 have been removed, the layer of polyl is removed with an anisotropic etch.
As stated above, since the polysilicon etching chemistries are highly selective with respect to oxides, if the oxide wedges 38 are not removed with the previous etching step, the oxide wedges 38 function as masks which prevent the polyl anisotropic etch from removing the polyl material which lies below the oxide wedges 38. Thus, as shown in FIG. 2E, the minimum thickness R of the combined layers of differential oxide 34 and edge oxide 32 must be greater than the combined thickness T of the oxide wedges 38 and the layers of differential oxide 34, edge oxide 32 and ONO 26.
Based on the above, it would appear that the problems presented by oxide thinning can be simply solved by merely insuring that the combined thickness R is greater than the combined thickness T. Referring to FIG. 2H, the problem with this approach, however, is that the oxidation process which is utilized to form the layer of differential oxide 34 also diffuses the N+ buried bit lines 30, thereby reducing the channel length CL of the resulting memory cells. Thus, if the differential oxide fabrication time is extended to insure that the thickness R is greater than the thickness T, the channel lengths CL of the resulting memory cells are substantially reduced.
Therefore, there is a need for an EPROM/flash fabrication process which eliminates oxide thinning, thereby eliminating the formation of the poly2 remnants, and increasing the thickness R of the combined layers of differential oxide 34 and edge oxide 32 without reducing the channel length of the memory cells, which, in turn, would allow the oxide wedges to be removed without etching away a portion of the N+ buried bit lines 30.